Senior FPGA / ASIC SoC Design Engineer

Oslo / Full-Time

Graphcore has created a completely new processor, the Intelligence Processing Unit (IPU), specifically designed for artificial intelligence. The IPU’s unique architecture means developers can run current machine learning models’ orders of magnitude faster. More importantly, it lets AI researchers undertake entirely new types of work, not possible using current technologies, to drive the next great breakthroughs in general machine intelligence.

We believe our IPU technology will become the worldwide standard for artificial intelligence compute. The performance of Graphcore’s IPU is going to be transformative across all industries and sectors whether you are a medical researcher, roboticist or building autonomous cars.

Our team is at the forefront of the artificial intelligence revolution, enabling innovators from all industries and sectors to expand human potential with technology. What we do, really makes a difference.

As a senior FPGA / ASIC design engineer, you will be working as part of Graphcore’s engineering team in Oslo developing Graphcore scale out technology for our Intelligence Processing Unit (IPU). In your work you will interact closely with the software and hardware teams to develop core IP and related components for our scale out technology.

In this role you will be responsible for development and integration of interconnect IP for our scale out AI and ML systems. This includes specification, architecture, design and implementation. You will also be involved in IP integration such as state of the art SerDes technology, SoC design, and system bring-up.

Requirements

  • A solid background and expertise in FPGA/ASIC design and verification.
  • A deep understanding of computer architecture and a solid HDL design and verification background is required
  • Good understanding of System on a Chip design and architecture
  • A background in high-speed network protocols such as Ethernet, PCIe, and IB will be an advantage
  • Solid experience in high-speed RTL design and verification, preferably Verilog/System Verilog is required
  • Experience with implementation tools such as Mentor tools, Synopsys DC and IC Compiler, Xilinx Vivado for FPGA design, Static timing analysis tools and constraint generation tools

Experience in international standardization work or knowledge of new interconnect standards is a plus. The position will work in a strong team with close interaction with colleagues in Bristol.

This is a full time role based in Oslo (Norway).

Key Skills

  • A solid background and expertise in FPGA/ASIC design and verification
    • A deep understanding of computer architecture and a solid HDL design and verification background is required
    • Solid experience in high-speed RTL design and verification, preferably Verilog/System Verilog is required

 

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